A spin transfer torque magnetic random access memory (STT-MRAM) device, which includes an array of densely packed STT-MRAM cells, is currently extensively explored for nonvolatile high-density data storage, since it exhibits non-volatility the same as a hard disk drive (HDD), a density as high as a dynamic RAM (DRAM) device, and a speed as fast as a static RAM (SRAM) device. In each STT-MRAM cell, a magnetic tunnel junction (MTJ) element, which mainly includes a nonmagnetic insulating barrier layer sandwiched between a ferromagnetic reference layer and a ferromagnetic storage layer, is integrated with a complementary metal-oxide-semiconductor (CMOS) transistor for write and read operations.
During the write operation of a conventional in-plane MTJ (iMTJ) element used in the STT-MRAM cell with a technology node of >90 nanometer (nm), the magnetization of the reference layer is rigidly pinned by an antiferromagnetic pinning layer in its plane, while the magnetization of the storage layer can be freely switched in its plane by a spin-transfer-torque (STT) into a direction parallel or antiparallel to that of the reference layer. The STT switching occurs when a write current passes through the iMTJ element and causes spin-polarized electrons to transfer a part of its angular momentum to and exert a torque on the magnetization of the storage layer. It is crucial to minimize a critical switching current density (JC) to below 105 amperes per square centimeter (A/cm2) for preventing the barrier layer from dielectric breakdown while maintaining effective STT switching.
During the read operation of a conventional iMTJ element, a read current passes through the iMTJ element and causes electrons to quantum-jump across the barrier layer. Scattering of electrons at lower and upper interfaces of the barrier layer induces a tunneling magnetoresistance (TMR) effect. When the magnetization of the storage layer is switched into a direction parallel to that of the reference layer, scattering is the lowest and the iMTJ element exhibits a minimal resistance (RO). When the magnetization of the storage layer is switched into a direction antiparallel to that of the reference layer, scattering is the highest and the iMTJ element exhibits a maximal resistance (RO+ΔRT), where ΔRT is the maximum tunnel magnetoresitance. To distinctly separate distributions of the two magnetizations states, coded as “0” and “1”, it is crucial to maximize a TMR coefficient (ΔRT/RO) beyond 100%.
On the other hand, during the write operation of an advanced perpendicular (pMTJ) element used in the STT-MRAM cell with a technology node of <90 nm, the magnetization of the reference layer is strongly magnetized in a direction perpendicular to its plane, while the magnetization of the storage layer can be freely switched out of its plane by the STT switching into a direction parallel or antiparallel to that of the reference layer. By replacing the iMTJ with pMTJ elements, the STT switching becomes more effective so that JC can be further minimized and the technology node can be further reduced. To properly perform the write operation with the pMTJ element, its reference and storage layers require specific polycrystalline structures and textures for attaining a high perpendicular magnetic anisotropy (PMA).
The read operation of the pMTJ element is basically identical to that of the iMTJ element. To properly perform the read operation with the pMTJ element, its reference, barrier and storage layers require different specific polycrystalline structures and textures for attaining a high ΔRT/RO.
In addition, a buffer layer which is sandwiched between a first interconnect and the pMTJ element has its own polycrystalline structure and texture. Mismatches at interfaces of different polycrystalline structures and textures may cause difficulties in attaining the desired high PMA and ΔRT/RO. Furthermore, after annealing at high temperatures, diffusions may occur at interfaces of different polycrystalline structures and textures and thus further deteriorate the PMA and ΔRT/RO.
FIG. 1 shows the schematic cross-sectional view of an STT-MRAM cell 100 in accordance with a prior art and the invention. The STT-MRAM cell 100 includes a CMOS transistor 110, a first interconnect 120, a bottom-type perpendicular magnetic tunnel junction (pMTJ) element 130, a second interconnect 140 and an insulator 150. The CMOS transistor 110 includes a p-type semiconductor substrate 112, a source 114, a drain 116, a floating gate 117 and a control gate 118. The first interconnect 120 comprises a lower stud 122, an upper stud 124 formed on top of the lower stud 122, and a diffusion barrier layer 126 formed on top of the upper stud 124. The pMTJ element 130 is formed on top of the diffusion barrier layer 126 and the second interconnect 140 is formed on top of the pMTJ 130. The insulator 150 is formed above the source 114, the drain 116, and the control gate 118, the diffusion barrier layer 126, and the second interconnect 140.
In the prior art, the lower stud 122 is formed of a nonmagnetic tungsten (W) film, the upper stud 124 is formed of a nonmagnetic copper (Cu) film, and the diffusion barrier layer 126 is formed of a nonmagnetic tantalum nitride (TaNx) film. The pMTJ element 130 is electrically connected to the first interconnect 120 and the second interconnect 140, but is electrically insulated by the insulator 150. During the write or read operation of the pMTJ element 130, the insulator 150 confines a write or read current to flow through the first interconnect 120, the pMTJ element 130 and the second interconnect 140 (or vice versa).
It is understood that only one bottom-type pMTJ element 130 is shown in the STT-MRAM cell 100 and discussed herein merely in the interest of brevity, and that numerous such pMTJ elements 130 in the STT-MRAM cell 100 are contemplated.
FIG. 2 shows the schematic cross-sectional view of a bottom-type pMTJ element 130/200 in accordance with the prior art. The bottom-type pMTJ element 200 typically comprises an electrically insulating barrier layer 240 sandwiched between a lower stack 220 and an upper stack 260. The barrier layer 240 is formed of a 1.2 nm thick nonmagnetic MgO film. When the read current quantum jumps across the barrier layer 240, changes in the electrical resistance are detected due to a tunneling magnetoresistance (TMR) effect.
The lower stack 220 comprises a buffer layer 222 formed of a 4 nm thick nonmagnetic Ta film, a seed layer 224 formed of a 4 nm thick nonmagnetic Pd film, a keeper layer 226 formed of [Co(0.2)/Pd(0.8)]×8/Co(0.4) (thickness in nm) films, a spacer layer 228 formed of a 0.8 nm thick nonmagnetic Ru film, a lower reference layer 230 formed of ferromagnetic Co(0.4)/Pd(0.8)/[Co(0.2)/Pd(0.8)]×2 films, and an upper reference layer 232 formed of a 0.8 nm thick ferromagnetic 60Fe-20Co-20B (composition in atomic percent) film.
The upper stack 260 comprises a storage layer 262, a lower cap layer 264, and an upper cap layer 266. The storage layer 262 is formed of a 1.2 nm thick ferromagnetic 60Fe-20Co-20B film, the lower cap layer 264 is formed of a 1.2 nm thick nonmagnetic MgO film, and the upper cap layer 266 is formed of a 80 nm thick nonmagnetic Ta film.
In the fabrication process of the STT-MRAM cell 100, the bottom-type pMTJ element 200 is deposited on a wafer onto which the CMOS transistor 110 and the first interconnect 120 is previously formed. The wafer is then annealed with a magnetic field of 10,000 Oe for 2 hours at 320° C. in a direction perpendicular to the wafer in a high-vacuum oven. The bottom-type pMTJ element 200 is then patterned in a photolithographic process to produce a feature size. After protecting the bottom-type pMTJ element 200 with insulation layers 150 and opening a via, the second interconnect 140 is deposited. The fabrication process then continues for multilevel interconnections and packaging.
To properly perform the write operation with the bottom-type pMTJ element 220, the magnetizations of the keeper layer 226, the lower reference layer 230, the upper reference layer 232 and the storage layer 262 must exhibit strong PMA. To exhibit strong PMA, the Co/Pd multilayer films used as the keeper layer 226 and the lower reference layer 230 must exhibit an fcc <111> texture, while the Fe—Co—B films used as the upper reference layer 232 and the storage layer 262 must be ultrathin and contact with the MgO film used as the barrier layer 240.
To properly perform the read operation with the bottom-type pMTJ element 220, a high ΔRT/RO is needed. To exhibit the high ΔRT/RO, an amorphous structure in the Fe—Co—B film used as the upper reference layer 232 must be transformed into a bcc structure with a <001> texture during annealing, which facilitates the barrier layer 240 and the storage layer 262 to also develop <001> textures and thus establish a Co—Fe—B<001>/MgO<001>/Co—Fe—B<001> epitaxial relationship needed for coherent tunneling. Due to a mismatch between the fcc <111> texture needed for the Co/Pd multilayer films and the bcc <001> texture needed for the Co—Fe—B film, the ΔRT/RO is still not high enough to properly perform the read operation.
It should be noted that the first interconnect 120 comprises a diffusion barrier layer 126 formed of a 8 nm thick TaNx film used to prevent an underlying Cu stud 124 from diffusions. This diffusion barrier layer 126 may cause the overlying Ta buffer layer 222 to develop a bcc <110> texture. Due to a mismatch between the bcc <110> texture developed in the Ta buffer layer 222 and the fcc <111> texture needed for the Pd seed layer 224 and the Co/Pd multilayer films, the keeper layer 226 and the lower reference layer 230 may not exhibit the fcc <111> texture strong enough to develop the needed PMA. Accordingly, there is a need of eliminating the mismatches and diffusions at interfaces of different polycrystalline structures and textures in order for the pMTJ element to exhibit the desired high PMA and ΔRT/RO.
Accordingly, a bottom-type perpendicular MTJ (pMTJ) element with thermally stable amorphous blocking layers, which eliminate the mismatches and diffusions at interfaces of different polycrystalline structures and textures is needed.